Authors
Malchukov A.
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Degree
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PhD in Technique, National research Tomsk Polytechnic University |
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E-mail
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1man@tpu.ru |
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Location
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Tomsk |
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Articles
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Fast checksum (CRC) calculation: table vs matrixIn this paper we consider fast matrix-driven algo¬rithm for computing the checksum on the examples: CRC8 and CRC32. This algorithm is easy to imple¬ment in combinational circuits and does not require storage device in the hardware implementation. The proposed algorithm requires less memory with its software implementation in contrast to table-driven implementation, especially in the processing of two, three or more bytes of data per cycle. A comparative analysis of the table-driven and the proposed matrix-driven algorithms is done and recommendations on the use of a matrix algorithm for computing the checksum CRC are given. Read more...Fast decoder of BCH code (15, 7, 5) structure development based on cyclic decoding method
The paper is about structure development of the fast BCH decoder (15, 7, 5) based on modified cyclic
decoding method. Cyclic decoding method based on iterative process of division by modulo 2 of
codeword by generator polynomial [21]. Decoder are presented in paper [2, 3] has low performance
and the main purpose of the paper is improving decoding speed using cyclic decoding method. For
the purpose it is necessary to perform tasks such as parallel computation of syndromes (remainder of
division of codeword by generator polynomial) and matrix algorithm of polynomial division implementation.
The principle of matrix algorithm is vector by matrix multiplication wherein codeword
acts as a vector, and matrix is pre-calculated matrix of predetermined lengths of the codewords and
generator polynomials. The codewords are generated in parallel for each shift and is sent to weights
computation block. The weight of codeword is computed for each codeword in parallel. The decoding
block receives weights, codewords and remainders and adds by modulo 2 codeword and remainder
the weight of which satisfied the condition weight <= t, where t is error count. Thus, proposed structure
of high-speed BCH code decoder, based on the modified cyclic method for decoding, can decode
for 1 – 2 clock cycles and improves performance to ~1182 times.
Read more...
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